The Workbook

1. D conducts when its anode (left) is positive, that is, during the positive half cycles. \(V_{out}\) is a series of positive half sine waves with gaps of zero between them.

2. One pulse per input cycle: \(50\) Hz.

3. The current through \(R_L\) always flows the same way, even though its size changes. Direct means one direction, not constant.

1. The two ends of the secondary are always of opposite polarity with respect to the centre tap. In one half cycle the upper end is positive and \(D_1\) conducts; in the next the lower end is positive and \(D_2\) conducts. Both diodes feed the same end of the load, so the current through \(R_L\) is always in the same direction.

2. Both halves of each cycle give a pulse: \(2 \times 50 = 100\) Hz.

1. Two, in series with the load, on opposite arms of the bridge. The other two are reverse biased.

2. The whole secondary voltage is used in each half cycle, so the peak output is twice that of a centre-tap circuit with the same transformer. No centre tap is needed. (Against this, two forward drops are lost instead of one.)

1. \(V_p = \sqrt{2} \times 10 = 14.1\) V.

2. Half-wave: one diode in the path, \(14.1 - 0.7 = 13.4\) V. Bridge: two diodes conduct in series, \(14.1 - 1.4 = 12.7\) V.

Half-wave: \(\dfrac{14.1}{\pi} \approx 4.5\) V. Full-wave: \(\dfrac{2 \times 14.1}{\pi} \approx 9.0\) V.

The half-wave output is zero for half the time. The full-wave circuit fills those gaps with the inverted negative half cycles, so the average over a cycle doubles.

1. Near each peak the diode conducts and charges the capacitor to nearly \(V_p\). When the input falls, the diode stops conducting and the capacitor discharges slowly through \(R_L\), holding the output up until the next peak. The dips are filled in.

2. \(R_L C = 10^{3} \times 10^{-4} = 0.1\) s. Full-wave peaks are \(10\) ms apart. \(0.1\) s is ten times longer, so the capacitor loses only a small part of its charge between peaks.

1. Peak \(14\) V. Peaks at \(5\), \(15\), \(25\) ms: \(10\) ms apart, so the output frequency is \(100\) Hz. A full-wave rectifier doubles the frequency, so the input is \(50\) Hz.

2. The dashed line falls from \(14\) V to about \(12\) V before each new peak recharges the capacitor. The ripple is about \(2\) V.

3. Use a larger \(C\) or a larger \(R_L\) (a smaller load current), so that \(R_L C\) is longer and the capacitor discharges less between peaks.

Diode towards the load: it conducts for positive inputs only. Output: the positive half cycles, \(0\) to \(10\) V, with zero during the negative halves.

Diode reversed: it conducts for negative inputs only. Output: the negative half cycles, \(0\) to \(-10\) V, zero during the positive halves.

1. The diode conducts when its anode is above its cathode, which sits at \(+3\) V. So it conducts when \(V_{in} > 3\) V. Then the output is held at \(3\) V; the excess voltage appears across \(R\).

2. When \(V_{in} < 3\) V the diode is off and no current flows through \(R\). \(V_{out} = V_{in}\).

3. The sine wave with its positive peaks cut flat at \(+3\) V. The negative half cycles are untouched and reach \(-10\) V.

The diode needs \(0.7\) V across it to conduct, so it turns on when \(V_{in} = 3 + 0.7 = 3.7\) V. The output is clipped at \(3.7\) V.

The upper branch conducts when \(V_{in} > 5\) V and holds the output at \(+5\) V. The lower branch conducts when \(V_{in} < -5\) V and holds it at \(-5\) V. In between, \(V_{out} = V_{in}\).

The output is the sine wave with both peaks cut flat: maximum \(+5\) V, minimum \(-5\) V.

1. A clipper cuts off part of the wave and changes its shape. A clamper keeps the shape but shifts the whole wave up or down, adding a dc level.

2. The capacitor charges to \(10\) V on the first negative peak and then acts as a \(10\) V battery in series. The output is \(10\sin\omega t + 10\), swinging from \(0\) to \(+20\) V.

1. Forward: an ordinary diode curve rising after \(0.7\) V. Reverse: almost no current until \(-V_Z\), then the current rises very steeply while the voltage stays at \(-V_Z\). The reverse curve is nearly vertical at \(V_Z\).

2. The reverse curve is nearly vertical: a large change in current needs only a tiny change in voltage. So however much current flows (within limits), the voltage stays at \(V_Z\).

3. Heavy doping makes the depletion region very thin, so even a few volts give a very strong electric field across it. The field can then pull electrons out of the bonds (Zener breakdown) at a low, well-defined voltage.

1. The Zener holds its side at \(6\) V, so \(R_s\) has \(12 - 6 = 6\) V across it. \(I_s = \dfrac{6}{200} = 30\) mA.

2. \(I_L = \dfrac{6}{600} = 10\) mA. The rest goes through the Zener: \(I_Z = 30 - 10 = 20\) mA.

3. \(P_Z = V_Z I_Z = 6 \times 0.020 = 0.12\) W.

\(I_s = \dfrac{15 - 6}{200} = 45\) mA. \(I_L\) is still \(\dfrac{6}{600} = 10\) mA. \(I_Z = 45 - 10 = 35\) mA.

The output stays at \(6\) V. The Zener absorbs the whole increase in current; that is how it regulates.

1. With \(I_Z = 5\) mA and \(I_L = 10\) mA, \(I_s = 15\) mA. Then \(V_{in} = 6 + 200 \times 0.015 = 9\) V. Below this the Zener leaves breakdown and the output falls.

2. \(I_{Z,\max} = \dfrac{0.3}{6} = 50\) mA, so \(I_s = 60\) mA and \(V_{in} = 6 + 200 \times 0.060 = 18\) V.

1. \(I_L = \dfrac{6}{300} = 20\) mA. \(I_s\) is still \(30\) mA, so \(I_Z = 10\) mA.

2. \(I_L\) would be \(\dfrac{6}{150} = 40\) mA, more than the \(30\) mA that \(R_s\) can supply at \(6\) V. The Zener current would be negative, which is impossible. The Zener switches off and \(R_s\), \(R_L\) form a plain divider: \(V_{out} = 12 \times \dfrac{150}{350} \approx 5.1\) V.

Zener breakdown: heavy doping, a very thin depletion layer, a strong field that pulls electrons directly out of bonds (tunnelling). Occurs below about \(5\) V. \(V_Z\) falls slightly as temperature rises (negative coefficient).

Avalanche breakdown: lighter doping, a wider depletion layer. A minority carrier is accelerated by the field, knocks out more carriers, and the numbers multiply like an avalanche. Occurs above about \(6\) V. \(V_Z\) rises slightly with temperature (positive coefficient). Between \(5\) and \(6\) V both act, and the coefficient is nearly zero.

1. In forward bias electrons and holes are pushed into the junction and recombine. Each recombination releases the gap energy \(E_g\), and in a suitable material this energy leaves as a photon.

2. \(\lambda = \dfrac{1240}{1.9} \approx 653\) nm: red.

3. \(E_g = \dfrac{1240}{470} \approx 2.6\) eV.

4. Silicon has \(E_g = 1.1\) eV, which would give infrared light (\(1130\) nm), not visible. Also, in silicon the recombination energy goes mostly into heat, not photons. Compounds such as GaAs and GaN are used instead.

1. The resistor takes \(5 - 2 = 3\) V at \(20\) mA: \(R = \dfrac{3}{0.020} = 150\ \Omega\).

2. \(P_R = 3 \times 0.020 = 60\) mW. \(P_{LED} = 2 \times 0.020 = 40\) mW.

3. The LED would have \(5\) V across it. Its forward current rises very steeply above \(2\) V, so a huge current would flow and burn it out at once. The resistor limits the current.

1. In reverse bias the dark current is tiny, so the extra current made by light stands out and is proportional to the light intensity. In forward bias the large ordinary current would swamp the small photocurrent.

2. The photon energy must be at least the band gap, \(h\nu \ge E_g\), so that it can create an electron-hole pair.

3. \(\lambda_{\max} = \dfrac{1240}{1.1} \approx 1130\) nm, in the near infrared. All visible light is detected.

Electrons collected per second \(= 0.8 \times 10^{15} = 8 \times 10^{14}\).

\(I = 8 \times 10^{14} \times 1.6 \times 10^{-19} = 1.28 \times 10^{-4}\) A \(= 128\ \mu\)A.

1. Photons create electron-hole pairs in and near the depletion region. The built-in field there sweeps electrons to the n side and holes to the p side. The separated charges make the p side positive and the n side negative: a voltage appears with no battery.

2. Area \(= 100\) cm\(^2 = 0.01\) m\(^2\). Power in \(= 1000 \times 0.01 = 10\) W. Power out \(= 0.2 \times 10 = 2\) W.

LED: forward bias; electrical energy in; light out. Turns current into photons.

Photodiode: reverse bias; light in; a current proportional to the light out. Used to detect and measure light.

Solar cell: no bias; light in; electrical power out. Turns photons into current and voltage, the reverse of the LED.

1. (a) is the AND gate (flat back, round front). (b) is the OR gate (curved back, pointed front). (c) is the NOT gate (triangle with a small circle, the inversion bubble).

2. \(Y_1 = A \cdot B\), \(Y_2 = A + B\), \(Y_3 = \bar{A}\).

OR (\(Y = A + B\)): \(00 \to 0\), \(01 \to 1\), \(10 \to 1\), \(11 \to 1\). Output \(1\) if any input is \(1\).

AND (\(Y = A \cdot B\)): \(00 \to 0\), \(01 \to 0\), \(10 \to 0\), \(11 \to 1\). Output \(1\) only if all inputs are \(1\).

NOT (\(Y = \bar{A}\)): \(0 \to 1\), \(1 \to 0\).

(i) \(A + 0 = A\). (ii) \(A + 1 = 1\). (iii) \(A \cdot 0 = 0\). (iv) \(A \cdot 1 = A\). (v) \(A + A = A\). (vi) \(A \cdot \bar{A} = 0\): a thing and its opposite are never both true. (vii) \(A + \bar{A} = 1\): one of them is always true.

1. \(1 \cdot 0 + 1 = 0 + 1 = 1\).

2. \(1 \cdot 1 + 0 = 1 + 0 = 1\).

3. \(0 \cdot 0 + 0 = 0\).

1. AND is high only when both are high. A is high \(1\) to \(3\) s and \(5\) to \(7\) s; B is high \(2\) to \(4\) s and \(6\) to \(8\) s. Both are high from \(2\) to \(3\) s and from \(6\) to \(7\) s. The output is two pulses of \(1\) s.

2. OR is high when either is high: from \(1\) to \(4\) s and from \(5\) to \(8\) s. Two pulses of \(3\) s, low only for \(0\) to \(1\) s and \(4\) to \(5\) s.

3. Two pulses each, but the AND pulses are short and the OR pulses long.

1. The upper diode has \(5\) V on its anode and conducts, pulling Y up to \(5\) V across \(R\). The lower diode has \(0\) V on its anode and \(5\) V on its cathode: reverse biased, off. \(Y = 5\) V, logic \(1\).

2. Neither diode conducts. No current flows in \(R\), so \(Y\) sits at \(0\) V through \(R\): logic \(0\).

3. Output \(1\) if A or B (or both) is \(1\): an OR gate. \(00 \to 0\), \(01 \to 1\), \(10 \to 1\), \(11 \to 1\).

The input goes to the base, the output is taken from the collector, and a resistor joins the collector to the supply.

Input high: base current flows, the transistor turns fully on (saturates), and the collector is pulled down almost to \(0\) V. Output low.

Input low: no base current, the transistor is off, no current flows in the collector resistor, and the collector sits at the supply voltage. Output high. The output is always the opposite of the input.

NAND: an AND symbol with a bubble on the output. \(Y = \overline{A \cdot B}\). Table: \(00 \to 1\), \(01 \to 1\), \(10 \to 1\), \(11 \to 0\).

NOR: an OR symbol with a bubble on the output. \(Y = \overline{A + B}\). Table: \(00 \to 1\), \(01 \to 0\), \(10 \to 0\), \(11 \to 0\).

1. With both inputs equal to A: \(Y = \overline{A \cdot A} = \bar{A}\). Table: \(0 \to 1\), \(1 \to 0\). It is a NOT gate.

2. The first NAND gives \(\overline{A \cdot B}\). The second inverts it: \(\overline{\overline{A \cdot B}} = A \cdot B\). The whole circuit is an AND gate.

Use two NAND gates as NOT gates (inputs joined) to make \(\bar{A}\) and \(\bar{B}\). Feed these into a third NAND: \(Y = \overline{\bar{A} \cdot \bar{B}}\).

By De Morgan, \(\overline{\bar{A} \cdot \bar{B}} = \bar{\bar{A}} + \bar{\bar{B}} = A + B\). The circuit is an OR gate.

NOT: one NOR with its inputs joined, \(\overline{A + A} = \bar{A}\).

OR: a NOR followed by a NOR used as NOT, \(\overline{\overline{A + B}} = A + B\). Two gates.

AND: invert each input with a NOR-as-NOT, then NOR them: \(\overline{\bar{A} + \bar{B}} = A \cdot B\) by De Morgan. Three gates.

First theorem: \(\overline{A + B} = \bar{A} \cdot \bar{B}\). Second theorem: \(\overline{A \cdot B} = \bar{A} + \bar{B}\). To invert a whole expression, invert each term and swap \(+\) with \(\cdot\).

Check: \(00\): \(\overline{0} = 1\) and \(1 \cdot 1 = 1\). \(01\): \(\overline{1} = 0\) and \(1 \cdot 0 = 0\). \(10\): \(0\) and \(0 \cdot 1 = 0\). \(11\): \(0\) and \(0 \cdot 0 = 0\). The two columns agree in every row.

Every logic function can be written with AND, OR and NOT. Questions 9 to 11 show that each of these three can be built from NAND gates alone, or from NOR gates alone. So any circuit at all can be built from one type of gate. That is why NAND and NOR are called universal.

1. \(\overline{\bar{A} + \bar{B}} = \bar{\bar{A}} \cdot \bar{\bar{B}} = A \cdot B\).

2. \(\overline{\bar{A} \cdot \bar{B}} = A + B\).

3. Two inversions cancel: \(A \cdot B\).

1. \(A + A \cdot B = A(1 + B) = A \cdot 1 = A\). If A is \(1\) the output is \(1\) whatever B is; if A is \(0\) both terms are \(0\). No gate is needed; the output is just A.

2. \(A \cdot B + A \cdot \bar{B} = A(B + \bar{B}) = A \cdot 1 = A\). Again just A.

3. With \(B = 1\): \((A + 1) \cdot \bar{A} = 1 \cdot \bar{A} = \bar{A}\). A NOT gate.

1. The AND gives \(A \cdot B\), the NOT gives \(\bar{C}\), and the OR combines them: \(Y = A \cdot B + \bar{C}\).

2. \(Y = 1\) whenever \(C = 0\) (four rows). When \(C = 1\), \(Y = A \cdot B\), which is \(1\) only for \(A = B = 1\). So \(Y = 0\) for \((0,0,1)\), \((0,1,1)\) and \((1,0,1)\): three of the eight rows.

Each input can be \(0\) or \(1\), so \(n\) inputs give \(2^n\) combinations. That is \(4\) rows for \(2\) inputs, \(8\) for \(3\) and \(16\) for \(4\).

1. Only for \(A = B = C = 1\): one row out of eight.

2. Only for \(A = B = C = 0\): one row out of eight.

3. They agree only for \(000\) (both \(0\)) and \(111\) (both \(1\)). For the other six rows OR gives \(1\) and AND gives \(0\). Two rows.

1. NAND is the opposite of AND. AND was high \(2\) to \(3\) s and \(6\) to \(7\) s. NAND is high everywhere else: \(0\) to \(2\), \(3\) to \(6\) and \(7\) to \(8\) s.

2. NOR is the opposite of OR. OR was low only \(0\) to \(1\) s and \(4\) to \(5\) s, so NOR is high exactly there.

1. \(00 \to 0\), \(01 \to 1\), \(10 \to 1\), \(11 \to 0\). \(Y = 1\) when the inputs are different, and \(0\) when they are the same. Unlike OR, both inputs high gives \(0\).

2. Two NOT gates for \(\bar{A}\) and \(\bar{B}\), two AND gates for \(A \cdot \bar{B}\) and \(\bar{A} \cdot B\), and one OR gate to add them. Five gates.

1. In series the lamp lights only when both switches are closed: AND.

2. In parallel the lamp lights when either switch is closed: OR.

The warning needs E true and S false: \(W = E \cdot \bar{S}\).

A NOT gate makes \(\bar{S}\) from the belt signal, and an AND gate combines it with E. Check: \(E = 1\), \(S = 0\) gives \(1 \cdot 1 = 1\); belt fastened, \(S = 1\), gives \(1 \cdot 0 = 0\).

1. \(0 + 0 = 00\): \(S = 0\), \(C = 0\). \(0 + 1 = 01\): \(S = 1\), \(C = 0\). \(1 + 0 = 01\): \(S = 1\), \(C = 0\). \(1 + 1 = 10\): \(S = 0\), \(C = 1\).

2. \(S\) is \(1\) only when the inputs differ: XOR. \(C\) is \(1\) only when both are \(1\): AND. This pair of gates is called a half adder.

Row \(00\): \(0 + 1 \cdot 0 = 0\) and \(0 + 0 = 0\). Row \(01\): \(0 + 1 \cdot 1 = 1\) and \(0 + 1 = 1\). Row \(10\): \(1 + 0 \cdot 0 = 1\) and \(1 + 0 = 1\). Row \(11\): \(1 + 0 \cdot 1 = 1\) and \(1 + 1 = 1\).

The two sides agree in all four rows, so \(A + \bar{A} \cdot B = A + B\). In words: if A is already true, B does not matter; if A is false, the result is just B.